新型半桥功率集成电路的研究
|
摘要
微型化、智能化已经成为功率半导体的发展趋势，智能功率集成电路（SPIC）正是在这种趋势下得到了快速发展，目前SPIC已广泛应用于照明、工业控制、电子计算机、航空航天设备、国防电子产品、以及各种电子消费品，并已成为功率半导体领域最为活跃的研究方向之一。在当今倡导的节能型社会、以及电子设备小型化的发展趋势中，智能功率集成电路的功耗、成本、体积和可靠性已成为人们最为关注的问题。
本论文在探讨了国内外电力电子技术与SPIC技术的发展现状及趋势后，针对上述提到的问题进行了深入研究。基于陈星弼院士提出的“横向优化变掺杂（OPT-VLD）”理论及相关专利，设计了LDMOS器件及横向高低侧功率器件，提出了一种新型高压电平位移电路，同时研究了半桥功率IC中高压器件的隔离技术；本文的研究重点是无需传统电平位移电路的新型半桥功率IC，以及其低压电路与低压电源的实现方法；同时为了提高横向功率器件可靠性，本文还研究两种多数载流子同时导电的横向功率器件，并与单子器件进行了比较。本论文在高校博士点基金的支持下，主要完成了如下工作：
1．基于陈星弼院士提出的“OPT-VLD”理论及“横向低侧高压器件及高侧高压器件”中美专利，设计了用于半桥功率IC的LDMOS器件及横向高低侧LDMOS器件，并进行了流片实验；同时，本文还提出了一新型电平位移电路，采用有源电阻代替传统的多晶硅电阻，不仅减少了芯片面积，还提高了可靠性。
2．基于陈星弼院士的“一种半导体器件”的中美专利，研究了半桥功率IC中高低侧高压功率器件及电平位移电路中高压器件的隔离技术，实现了将四个高压器件制作于相邻的耐压区内，不仅减少了芯片面积，还解决了传统结构中的高压互连问题，在MEDICI和DAVINCI的仿真结果表明了其可行性。
3．提出了两种实现无需传统高压电平位移电路的新型半桥功率IC的方法。该两种方法均是采用片内感应信号的思想，通过在低侧n-LDMOS功率器件上集成一个高压PMOS，通过盆电路控制PMOS的开关而感应到一个脉冲信号，该脉冲信号经过一个低压电路处理后，便可用于控制低侧n-LDMOS功率器件。该方法无需传统的高压电平位移电路，不仅节省了可观的芯片面积，同时还降低了功耗以及消除了传统高压电平位移电路中的寄生效应，从而提高了可靠性。
4．设计了用于新型半桥功率IC的CMOS低压电路，主要包括脉冲信号发生器电路、死区时间控制电路；基于陈星弼院士的“低压电源”的中美专利，设计了用于低压电路的正电源及该低压电源的稳压器电路；除此之外，提出了一种新型欠压检测方法，并设计了相关电路；由于控制高压PMOS的栅极需要相对于盆电位为负的电源，因此还通过电路实现了将正电源转换为负电源，为PMOS栅极驱动电路提供电源。
5．基于陈星弼院士“一种半导体横向器件和高压器件”的中美专利，研究了两种载流子同时导电的LDMOS器件，而该器件为双栅、四端器件，为了方便应用和控制，提出了采用片内感应信号以控制其中一个栅极的方法，实现了将四端器件变为三端器件，并对所得到的三端np-LDMOS器件与n-LDMOS器件进行了对比研究。
Microminiaturization and intelligence have become the development trends ofpower semiconductors, and smart power IC (SPIC) has been developing rapidly withthese trends and now it has been widely used in lighting, industrial control, computer,aerospace equipment, defense electronics, and a variety of consumer electronics, whichhas become the most active research field of power semiconductors. In today's advocacyof energy-saving, as well as the trend electronic equipment microminiaturization, thepower consumption, cost, size and reliability of SPIC have become a matter of concernfor more and more people.
After discussing the status and development trends of domestic and foreign powerelectronic technologies and SPIC, the above-mentioned problems are studied in thisdissertation. Based on the―optimum variation lateral doping (OPT-VLD)‖theory andpatents which had been proposed by academician Chen Xingbi, LDMOS devices andlateral low side and high side power devices are designed in this dissertation. In themeantime, a new high-voltage level shifter circuit and the isolation technology for thehigh voltage devices of a half bridge power IC are also proposed. This dissertationfocuses on the novel half-bridge power IC without using the traditional high voltagelevel shift circuit, as well as its low-voltage CMOS circuit and low-voltage powersupply circuit realization methods. Moreover, in order to improve reliability of lateralpower devices, two lateral power devices with both types of majority carriers forconduction are also proposed. Base on the support of Ph.D. Programs Foundation of theMinistry of Education of China, the main work of the author is as follows:
1. Based on the―OPT-VLD‖theory and the patent of―lateral low-side andhigh-side high-voltage devices‖which had been proposed by academician Chen Xingbi,LDMOS devices and lateral low side and high side power devices are designed by theauthor. And an experimental frabrication was made to verify the devices. In themeantime, a new high-voltage level shifter circuit which utilizes active resistors tosubstitute the conventional polysilicon resistor is also proposed, thus the new levelshifter circuit not only saves chip area, but also improves its reliability.
2. Based on the patent "a semiconductor device" proposed by academician ChenXingbi, the isolation technology between the two high voltage high low side powerdevice and the two high-voltage devices of level shifter circuit is studied, and the fourhigh high-voltage devices can be fabricated in adjacent voltage sustaining area, which not only saves chip area, but also solves the high-voltage interconnection in theconventional structure. The solution is verified with MEDICI and DAVINCI, and thesimulation results show its feasibility.
3. Two methods of realizing a novel half-bridge power IC without utilizingconventional high voltage level shift circuit are proposed. The two methods are bothbased on the idea of sensing signals within the chip. Specifically, a high voltage PMOSis integrated in the low-side n-LDMOS power device, when the PMOS is switchedunder the controlling of the tub circuit a pulse signal is sensed, which can be used forcontrolling the low-side n-LDMOS after being processed by a low voltage circuit. Sincethe conventional high voltage level shifter circuit is no more needed in the newhalf-bridge power IC, not only saves considerable chip area, but also reduces powerconsumption and eliminate parasitic effects of traditional high voltage level shift circuit,which increases the reliability of the power IC.
4. The CMOS low-voltage circuits of the half-bridge power IC which includingpulse signal generator and dead-time control circuit are designed. In the meantime, thepositive low voltage power supplies for the CMOS circuits and a new undervoltagedetection method with relevant circuit are also proposed, based on the patent "lowvoltage power supply" of proposed by academician Chen Xingbi. In order to improvethe performance of the positive low voltage power supply, a voltage regulator circuit isalso presented. Since the control voltage of the PMOS’ gate driving circuit is negativereferred to the tub voltage, thus a circuit for transforming the positive low voltagepower supply to a negative low voltage power supply is also proposed, and the obtainednegative low voltage power supply can be used for providing energy for the PMOS’gate driving circuit.
5. Based on the patent of "a semiconductor lateral device and a high-voltagedevice" which proposed by academician Chen Xingbi, the LDMOS device with bothtypes of majorities for conduction is studied. Commonly, the device is a dual-gate,four-terminal device. Thus, in order to change the four-terminal device to three-terminalone, two methods with sensing a control signal inside the chip are proposed. Moreover,a comparative study between the three-terminal np-LDMOS and the n-LDMOS is alsoproposed in this dissertation.
本论文在探讨了国内外电力电子技术与SPIC技术的发展现状及趋势后，针对上述提到的问题进行了深入研究。基于陈星弼院士提出的“横向优化变掺杂（OPT-VLD）”理论及相关专利，设计了LDMOS器件及横向高低侧功率器件，提出了一种新型高压电平位移电路，同时研究了半桥功率IC中高压器件的隔离技术；本文的研究重点是无需传统电平位移电路的新型半桥功率IC，以及其低压电路与低压电源的实现方法；同时为了提高横向功率器件可靠性，本文还研究两种多数载流子同时导电的横向功率器件，并与单子器件进行了比较。本论文在高校博士点基金的支持下，主要完成了如下工作：
1．基于陈星弼院士提出的“OPT-VLD”理论及“横向低侧高压器件及高侧高压器件”中美专利，设计了用于半桥功率IC的LDMOS器件及横向高低侧LDMOS器件，并进行了流片实验；同时，本文还提出了一新型电平位移电路，采用有源电阻代替传统的多晶硅电阻，不仅减少了芯片面积，还提高了可靠性。
2．基于陈星弼院士的“一种半导体器件”的中美专利，研究了半桥功率IC中高低侧高压功率器件及电平位移电路中高压器件的隔离技术，实现了将四个高压器件制作于相邻的耐压区内，不仅减少了芯片面积，还解决了传统结构中的高压互连问题，在MEDICI和DAVINCI的仿真结果表明了其可行性。
3．提出了两种实现无需传统高压电平位移电路的新型半桥功率IC的方法。该两种方法均是采用片内感应信号的思想，通过在低侧n-LDMOS功率器件上集成一个高压PMOS，通过盆电路控制PMOS的开关而感应到一个脉冲信号，该脉冲信号经过一个低压电路处理后，便可用于控制低侧n-LDMOS功率器件。该方法无需传统的高压电平位移电路，不仅节省了可观的芯片面积，同时还降低了功耗以及消除了传统高压电平位移电路中的寄生效应，从而提高了可靠性。
4．设计了用于新型半桥功率IC的CMOS低压电路，主要包括脉冲信号发生器电路、死区时间控制电路；基于陈星弼院士的“低压电源”的中美专利，设计了用于低压电路的正电源及该低压电源的稳压器电路；除此之外，提出了一种新型欠压检测方法，并设计了相关电路；由于控制高压PMOS的栅极需要相对于盆电位为负的电源，因此还通过电路实现了将正电源转换为负电源，为PMOS栅极驱动电路提供电源。
5．基于陈星弼院士“一种半导体横向器件和高压器件”的中美专利，研究了两种载流子同时导电的LDMOS器件，而该器件为双栅、四端器件，为了方便应用和控制，提出了采用片内感应信号以控制其中一个栅极的方法，实现了将四端器件变为三端器件，并对所得到的三端np-LDMOS器件与n-LDMOS器件进行了对比研究。
Microminiaturization and intelligence have become the development trends ofpower semiconductors, and smart power IC (SPIC) has been developing rapidly withthese trends and now it has been widely used in lighting, industrial control, computer,aerospace equipment, defense electronics, and a variety of consumer electronics, whichhas become the most active research field of power semiconductors. In today's advocacyof energy-saving, as well as the trend electronic equipment microminiaturization, thepower consumption, cost, size and reliability of SPIC have become a matter of concernfor more and more people.
After discussing the status and development trends of domestic and foreign powerelectronic technologies and SPIC, the above-mentioned problems are studied in thisdissertation. Based on the―optimum variation lateral doping (OPT-VLD)‖theory andpatents which had been proposed by academician Chen Xingbi, LDMOS devices andlateral low side and high side power devices are designed in this dissertation. In themeantime, a new high-voltage level shifter circuit and the isolation technology for thehigh voltage devices of a half bridge power IC are also proposed. This dissertationfocuses on the novel half-bridge power IC without using the traditional high voltagelevel shift circuit, as well as its low-voltage CMOS circuit and low-voltage powersupply circuit realization methods. Moreover, in order to improve reliability of lateralpower devices, two lateral power devices with both types of majority carriers forconduction are also proposed. Base on the support of Ph.D. Programs Foundation of theMinistry of Education of China, the main work of the author is as follows:
1. Based on the―OPT-VLD‖theory and the patent of―lateral low-side andhigh-side high-voltage devices‖which had been proposed by academician Chen Xingbi,LDMOS devices and lateral low side and high side power devices are designed by theauthor. And an experimental frabrication was made to verify the devices. In themeantime, a new high-voltage level shifter circuit which utilizes active resistors tosubstitute the conventional polysilicon resistor is also proposed, thus the new levelshifter circuit not only saves chip area, but also improves its reliability.
2. Based on the patent "a semiconductor device" proposed by academician ChenXingbi, the isolation technology between the two high voltage high low side powerdevice and the two high-voltage devices of level shifter circuit is studied, and the fourhigh high-voltage devices can be fabricated in adjacent voltage sustaining area, which not only saves chip area, but also solves the high-voltage interconnection in theconventional structure. The solution is verified with MEDICI and DAVINCI, and thesimulation results show its feasibility.
3. Two methods of realizing a novel half-bridge power IC without utilizingconventional high voltage level shift circuit are proposed. The two methods are bothbased on the idea of sensing signals within the chip. Specifically, a high voltage PMOSis integrated in the low-side n-LDMOS power device, when the PMOS is switchedunder the controlling of the tub circuit a pulse signal is sensed, which can be used forcontrolling the low-side n-LDMOS after being processed by a low voltage circuit. Sincethe conventional high voltage level shifter circuit is no more needed in the newhalf-bridge power IC, not only saves considerable chip area, but also reduces powerconsumption and eliminate parasitic effects of traditional high voltage level shift circuit,which increases the reliability of the power IC.
4. The CMOS low-voltage circuits of the half-bridge power IC which includingpulse signal generator and dead-time control circuit are designed. In the meantime, thepositive low voltage power supplies for the CMOS circuits and a new undervoltagedetection method with relevant circuit are also proposed, based on the patent "lowvoltage power supply" of proposed by academician Chen Xingbi. In order to improvethe performance of the positive low voltage power supply, a voltage regulator circuit isalso presented. Since the control voltage of the PMOS’ gate driving circuit is negativereferred to the tub voltage, thus a circuit for transforming the positive low voltagepower supply to a negative low voltage power supply is also proposed, and the obtainednegative low voltage power supply can be used for providing energy for the PMOS’gate driving circuit.
5. Based on the patent of "a semiconductor lateral device and a high-voltagedevice" which proposed by academician Chen Xingbi, the LDMOS device with bothtypes of majorities for conduction is studied. Commonly, the device is a dual-gate,four-terminal device. Thus, in order to change the four-terminal device to three-terminalone, two methods with sensing a control signal inside the chip are proposed. Moreover,a comparative study between the three-terminal np-LDMOS and the n-LDMOS is alsoproposed in this dissertation.
引文
[1]廖冬初,聂汉平.电力电子技术[M],武汉:华中科技大学出版社,2007:I-II
[2]王建冈.―电力电子技术‖课程教学初探[J].自动化与仪器仪表,2003,5:54-56
[3]王君.现代电子技术在电力系统中的应用分析[J].黑龙江科技信息,2010,06:1-2
[4]唐击.智能电网背景下大功率电力电子技术的巨大市场机遇[J].电器工业,2009,10:8-11
[5]樊立萍,王忠庆.电力电子技术[M].北京：北京大学出版社,2006,1-2
[6] J. Arai, K. Iba, T. Funabashi, Y. Nakanishi. Power electronics and its applications to renewableenergy in Japan[J]. Circuits and Systems Magazine,2008,8(3):52-66
[7] T. G. Wilson. The evolution of power electronics[J]. IEEE Trans. on Power Electronics,2000,15(3):439-446
[8] William E. Newell. Power electronics—emerging from limbo[J]. IEEE Transa. on IndustryApplications,1974, IA-10(1):7-11
[9] W. Erickson Robert, D. Maksimovic. Fundamentals of power electronics (2ndedition)[M].Publisher: Kluwer Academic,2001, Chapter1:3-4
[10]胡浩.智能功率集成电路中的部分模块研究[D].成都:电子科技大学,2012
[11] B. K. Bose. Recent advances in power electronics[J]. IEEE Transactions on Power Electronics,1992,7(1):2-16
[12] L. Lorenz, G. Deboy, A. Knapp. COOLMOS-a new milestone in high voltage powerMOS[C]. The11thInternational Symposium on Power Semiconductor Devices and ICs,Toronto,1999,3-10
[13]王青峰.基于软开关技术馈能性电子负载的研究[D].重庆:重庆大学.2007:9-10
[14] Y.Jang, M.M. Jovanovic, K.H. Fang, et al.. High-power-factor soft-switched boost converter[J].IEEE Transactions on Power Electronics.2006,21(1):98-104
[15] F. L. Luo, H. Ye, H. R. Muhammad. Digital power electronics and applications [DB], USA:Elsevier Academic Press,2005
[16] M. N. Yoder.Wide bandgap semiconductor materials and devices[J]. IEEE transactions onelectron devices.1996,43(10):1633-1636
[17] Wide bandgap semiconductors: pursuing the promise. Energy efficiency and renewableenergy[DB]. U.S. Department of Energy,April2013
[18] J. Milla′n.Wide band-gap power semiconductor devices[J].IET Circuits Devices Syst.,2007,1(5):372-378
[19] J.W. Kolar, J. Biela, S. Waffler, et al.. Performance trends and limitations of power electronicsystems[C]. The6thInternational Conference on Integrated Power Electronics Systems (CIPS),2010,1-20
[20] C. E. Mullett. A5-year power technology roadmap[C]. The19thIEEE Applied PowerElectronics Conference, Anaheim,2004,1:11-17
[21] L. Lorenz. Technology trends and application challenges of new power semiconductor devices
[DB]. Infineon Technologies,2010,1-8
[22] H. Umida. Power electronics technology trends and prospects[J]. Fuji Electric Journal,2002,75(8):1-5
[23]陈晨.电力电子技术发展动向与应用[J].电力电子.2013,9:53
[24]肖向锋.电力电子器件产业发展战略研究[J].电力电子.2011,1:6-9
[25] M. Kawano, J. Hirose, T. Aihara. Power electronics technology: current status and futureoutlook[J]. Power Electronics Technology,2012,58(4):142-148
[26] J. Arai, K. Iba, T. Funabashi, et al.. Power electronics and its applications to renewable energyin Japan[J]. Circuits and Systems Magazine,2008,8(3):52-66
[27] M. Molinas, O. Skjervheim, P. Andreasen, et al.. Power electronics as grid interface for activelycontrolled wave energy converters[C]. International Conference on Clean Electrical Power,2007,188-195
[28] J. Alok.power electronics and its applications (2ndEdition)[M]. India: Penram InternationalPublishing Pvt. Ltd.,2004
[29] B. Murari, F. Bertotti, G.A. Vignola (Eds.) Smart power ICs: technologies and applications (2ndedition)[M]. Berlin: Springer,2002
[30] B. K. Bose. Recent advances and applications of power electronics and motor drives-introduction and perspective[C]. Annual Conference of IEEE Industrial Electronics,2008,25-27
[31]李肇基.新型功率MOS器件及其应用[J].电子科技导报,1995,12:29-34
[32] Y. Tarui, Y. Hayashi, T. Sekigawa. Diffusion self aligned enhance depletion MOS IC (DSA-ED-MOS-IC)[J], Journal of the Japan Society of Applied Physics,1971,40:193-198
[33]雷珍琳,史中海,裴志军,等.平面栅功率MOS场效应晶体管结构研究进展[J].天津职业技术师范大学学报,2012,22(4):17-20
[34] J. A. Appels, H. M. J. Vaes. High voltage thin layer devices (RESURF devices)[C].1979IEEEInternational Electron Devices Meeting, Washington,1979,25:238-241
[35] A. Parpia, C. A. T. Salama. Optimization of RESURF LDMOS transistors: an analyticalapproach[J]. IEEE Transactions on Electron Devices,1990,37(3):789-796
[36] M. M. De Souza, E. M. S. Narayanan. Double RESURF technology for HVICs[J]. ElectronicsLetters,1996,32(12):1092-1093
[37] Z. Hossain, M. Imam, J. Fulton, et al.. Double-RESURF700V N-channel LDMOS withbest-in-class on-resistance[C]. In14thInternational Symposium on Power SemiconductorDevices and ICs,Sante Fe,2002,137-140
[38] X. B. Chen. Lateral high-voltage devices using an optimized variation lateral doping[J]. Int.J.Electronics,1996,80(3):449-459
[39] T. D. Tsibukis, and E. E. Kriezis. VVMOS power transistors: upper and lower bounds of theon-resistance[J]. Electronics Letters,1981:353-355
[40] E.S. Ammar, T.J. Rodgers. UMOS transistors on (110) silicon[J].IEEE Trans. Electron Devices,1980,27(5):907-914
[41] C. A. T. Salama. A new short channel MOSFET structure (UMOST)[J].Solid-State Electronics1977,20(12):1003-1009
[42] H. W. Collins, B. Pelly, HEXFET, A new power technology cuts on-resistance, boosts ratings[J].Electron Design,1979,17(12):36-37
[43]杨法明,杨发顺,张锗源,等.功率VDMOS器件的研究与发展[J].微纳电子技术,2011,48(10):623-629
[44] X. B. Chen, X. Wang, J. K. Sin. A novel high-voltage sustaining structure with buriedoppositely doped regions[J].IEEE Transactions on Electron Devices.2000,47(6):1280-1285
[45] D. Ueda, H. Takagi, and G. Kano. A new vertical power MOSFET structure with extremelyreduced on-resistance[J]. IEEE Transactions on Electron Devices,1985,32(1):2-6
[46] P. Wang, X. Luo, Y. Jiang, et al.. Ultra-low specific on-resistance vertical double-diffusedmetal—oxide semiconductor with a high-k dielectric-filled extended trench[J].Chinese PhysicsB,2013,22(2):027305-1～027305-6
[47] X. B. Chen. Semiconductor power devices with alternating conductivity type high-voltagebreakdown regions [P]. U.S. Patent,5216275,1Jun.1993
[48] G. Deboy, N. Marz, J. P. Stengl, et al.. A new generation of high voltage MOSFETs breaks thelimit line of silicon[C]. International Electron Devices Meeting, Sanfrancisco,1998,12:683-685
[49] L. Lorenz, I. Zverev, A. Mittal, et al.. CoolMOS-a new approach towards systemminiaturization and energy saving[C]. IEEE Industry Applications Conference,Rome,2000,5:2974-2981
[50]陈星弼.超结器件.电力电子技术[J],2008,42(12):2-7
[51] Yole Développement.Super junction MOSFET business update [OL]. http://www.i-micronews.com/reports/Super-Junction-MOSFET-Business-Update/12/344/, Feb.11,2013
[52] Y. Chen, Y. C. Liang, G. S. Samudra,et al.. Progressive development of superjunction powerMOSFET devices[J]. IEEE Transactions on Electron Devices,2008,55(1),211-219
[53] W. Saito, I. Omura, S. Aida, et al.. Over1000V semi-superjunction MOSFET with ultra-lowon-resistance below the si-limit[C]. In17thInternational Symposium on Power SemiconductorDevices and ICs, Santa Barbara,2005,27-30
[54]佘烁杰,杜倩倩,谢雪松,等. IGBT的进展、应用及其可靠性研究[C].2010第十五届可靠性学术年会论文集,2010,158-163
[55]王正元,宋高升. IGBT技术的发展历史和最新进展[J].电力电子,2004,(2)5:7-12
[56] L. Lindenmuller, R. Alvarez, P. Kleinichen, et al.. Characterization of a6.5kV/500A IGBTmodule in a series resonant converter[C]. In Energy Conversion Congress and Exposition(ECCE), Phoenix,2011,4138-4143
[57] M. M. Bakran, H. G. Eckel. Evolution of IGBT converters for mass transit applications[C].In IEEE Industry Applications Conference, Rome,2000,3:1930-1935
[58] V. Michael, C. Fazio, K. Hugh. Ultracompact pulsed power[J]. Proceedings of the IEEE,2004,92(7):1197-1204
[59]许平. IGBT器件新结构及制造技术的新进展[J].电力电子,2005,(3):21-26
[60] News about application specific power semiconductors part1attack of the IGBT[OL].http://www.analog-eetimes.com/en/application-specific-power-semiconductors-part-1-attack-of-the-igbt.html,July16,2010
[61] J. Yeon, M. Park.第2代FS SA T IGBT可显着减少单端谐振逆变器总损耗[OL].http://www.ednchina.com/ART_8800511843_28_20003_TA_59b45b48.HTM, May7,2013
[62] X. Kang, C. Antonio, S. Enrico, et al.. Characterization and modeling of high-voltagefield-stop IGBTs[J]. IEEE Transactions on Industry Applications,2003,39(4):922-928
[63] K. Oh, J. Lee, K. Lee, et al.. A simulation study on novel field stop IGBTs usingsuperjunction[J]. IEEE Transactions on Electron Devices,2006,53(4):884-890
[64] T. Tetsujiro. Method of manufacturing a semiconductor device of an anode short circuitstructure [P]. U.S. Patent,5286655, Feb.15,1994
[65] M. Saggio, V. Raineri, R. Letor, et al.. Innovative localized lifetime control in high-speedIGBTs[J]. Electron Device Letters,1997,18,(7):333-335
[66] J. Pike, A. Douglas, W. T. Dah Tsang, et al.. IGBT process to produce platinum lifetime control
[P].U.S. Patent,5262336, Nov.16,1993
[67] X. B. Chen. High speed IGBT [P]. U.S. Patent,0219446, Sep.25,2010(或陈星弼.一种高速IGBT [P].中国,发明专利,200910119961.3,2009年7月29日)
[68]于福振,吴玉广.智能功率模块及其应用[J].微电机,2003,1:52-55
[69] Intelligent Power Module Sets New Mark for Power Delivery [OL]. http://www.how2power.com/newsletters/0910/products/p1/index.html, Oct.2009
[70]许艳惠,李晓光,杨树臣.智能功率模块在电力机车中的应用[J].电力电子技术,2010,3:79-81.
[71] G. Majumdar. Recent technologies and trends of power devices[C]. International Workshop onPhysics of Semiconductor Devices,India,2007:787-792
[72]钱小工.Smart功率集成电路[J].半导体情报,1992,01:33-48
[73]李肇基,李鸿雁,方健,等.智能功率集成电路精彩纷呈[J]世界产品与技术,2000,6:12-15
[74]孙伟锋,张波,肖胜安,等.功率半导体器件与功率集成技术的发展现状及展望[J].中国科学:信息科学,2012,42(12):1617-1629
[75]刘继芝.高压电源管理芯片中低压电路用电源的研究[D].成都:电子科技大学,2009
[76] B. J. Baliga. An overview of smart power technology[J]. IEEE Transactions on ElectronDevices,1991,38(7):1568-1575
[77]陈志勇,黄其煜,龚大卫. BCD工艺概述[J].半导体技术,2006,31(9),641-644
[78] I. Park, Y. Choi, K. Ko, et al.. BCD (Bipolar-CMOS-DMOS) technology trends for powermanagement IC[C].2011IEEE8thInternational Conference on Power Electronics and ECCEAsia (ICPE&ECCE),Jenu,2011,318-325
[79]杨银堂,朱海刚. BCD集成电路技术的研究与进展[J],微电子学2006,36(3):315-319
[80] B. Murari, C. Contiero, R. Gariboldi,et al.. Smart power technologies evolution[C].2000IEEEIndustry Applications Conference, Europe,2000,1:10-19
[81] C. Contiero, P. Galbiati, A. Merlini, et al.. Trends and issues in BCD smart powertechnologies[C]. IEEE29thSolid-State Device Research Conference, Leuven,1999,1:111-118
[82] E. Dallago, A. Danioni, G. Ricotti, et al.. Single chip, low supply voltage piezoelectrictransformer controller[C]. IEEE29thSolid-State Circuits Conference,Europe,2003:273-276
[83] P. Wessels, M. Swanenberg, J. Claes, et al.. Advanced100V0.13μm BCD process for nextgeneration automotive applications[C]. IEEE18thInternational Symposium on PowerSemiconductor Devices&ICs, Naples,2006,315-318
[84] C. Contiero, A. Antonio, G. Paola. Roadmap differentiation and emerging trends in BCDtechnology[C]. In Proc. ESSDERC, Firenze,2002,275-282
[85] J. Chery. Sustainable Technology&Leadership[R].Technology report PPT of STMicroelectronics Corp.,2011:17-19
[86] M. Zisa. A smartpower innovative actuator in automotive field[C]. In FourteenthEuropean Solid-State Circuits Conference, Manchester,1988,284-290
[87] M. Melito, S. Palara, S. Sueri, et al.. Modern electronic ignition in VIPower technology[C]. InIEEE Intelligent Vehicles'94Symposium, Monterey,1994,435-437
[88] R. Zambrano, G. Fallico, G. Ferla. High voltage IC with vertical current flow and junctionisolation[C]. In IEEE19thSolid State Device Research Conference, Berlin,1989,523-526
[89] M. Melito, G. Belverde, A. Galluzzo, et al.. Bipolar-MOS monolithic cascode switch inVIPower technology[C].Industry Applications Society Annual Meeting, Denver,1994,1322-1325
[90] A. L. Barbera, A. Randazzo, V. Sueri, et al.. A monolithic electronic driver for fluorescentLAMPs[C]. In16thISPSD, Kitakyushu,2004,329-331
[91] X. B. Chen, Z. Q. Song, Z. J. Li Theory of optimum design of reversed-biased p-njunctionsusing resisitive field plates and variational lateral doping[J],Solid State Electronics,1992,35(9):1365-1370
[92] X. B. Chen. Lateral high-voltage devices using an optimized variational lateral doping[J].International journal of electronics,1996,80(3):449-459
[93] X. Chen, X. Fan. Optimum VLD makes SPIC better and cheaper[C].The6th InternationalConference on Solid-State and Integrated-Circuit Technology, Shanghai,2001,1:104-108
[94] X. B. Chen. Surface voltage sustaining structure for semiconductor devices[P].U.S.Patent,5726469, Mar.10,1998
[95]陈星弼.一种用于半导体器件的表面耐压区[P].中国,发明专利, CN1124408,1996年6月12
[96] Yole Développement. Status of the Power Electronics Industry [OL]. http://www.i-micronews.com/reports/Status-Power-Electronics-Industry/12/305/,August10,2012
[97] Yole Developpement.Power device market to bounce back in2013[OL]. http://www.eetimes.com/design/industrial-control/4410770/Power-device-market-to-bounce-back-in-2013,January20,2013
[98] Yole Développement. IGBT Markets and Application Trends Report, IGBT application growthwill lead the market to$6B+by2018[OL]. http://www.i-micronews.com/reports/IGBT-Markets-Trends/12/371/, June10,2013
[99] Yole Développement. SiC Market2013[OL]. http://www.i-micronews.com/reports/SiC-Market-2013/368/, May25,2013
[100] R. Philippe. Delayed progress hits SiC and GaN power device prospects [DB]. PowerDev.,2013,9:18-20
[101]2012年全球功率半导体市场规模比上年减少11.5％，将从2013年下半年开始复苏
[OL].http://china.nikkeibp.com.cn/news/tren/66063-20130520.html, May21,2013
[102] IMS Research.Market for gan and sic power semiconductors set to rise by factor of18from2012to2022[OL]. http://www.imsresearch.com/press-release/market_for_gan_and_sic_power_semiconductors_set_to_rise_by_factor_of_18_from_2012_to_2022, April24,2013
[103]吴琪乐.电子科技大学微固学院副院长张波谈功率器件[J].半导体信息,2011,6:28-29
[104] MOSFET工艺平台提升功率器件性能[OL]. http://semi.cena.com.cn/2013-02/26/content_186261.htm,2013年2月6日
[105]许力.半桥驱动芯片的分析与设计[D].成都:电子科技大学,2009
[106] T. Mishima, M. Nakaoka. A novel high-frequency transformer-linked soft-switchinghalf-bridge DC–DC converter with constant-frequency asymmetrical PWM scheme[J]. IEEETransactions on Industrial Electronics,2009,56(8):2961-2969
[107]毛兴武,刘雪琴.半桥驱动器IR2155电路的应用[J].广东电子,1996,3:33-35
[108]惠斌.一种高速高压半桥驱动电路的分析与设计[D].西安:西北大学,2010
[109] X. B. Chen. Lateral low-side and high-side high-voltage devices [P]. U.S. Patent,6998681, Feb.14,2006(或陈星弼.横向低侧高压器件及高侧高压器件[P].中国,发明专利, CN1529363,2004年9月15)
[110] D. W. Green, E. M. Sankara Narayanan. Fully isolated high side and low side LIGBTs injunction isolation technology[C]. IEEE International Symposium on Power SemiconductorDevices and IC's, Naples,2006,6:1-4
[111] Y. Takeuchi, Y. Takagi. Power IC having high-side and low-side switches in an SOI structure
[P]. U.S. Patent,5939755,17Aug,1999
[112] Y. Yan, Z. Regan. Dual low voltage IC based high and low side gate drive[C]. NineteenthAnnual IEEE Applied Power Electronics Conference, Austin,2004,2:1033-1038
[113] P. Shihong Park, M. Thomas, A. Jahns. A self-boost charge pump topology for a gate drivehigh-side power supply[J]. IEEE transactions on power electronics,2005,20(2):300-307
[114] J. J. Kim, M. H. Kim, S. L. Kim, et al.. The new high voltage level up shifter for HVIC[C].IEEE33rdAnnual Power Electronics Specialists Conference, Cairns,2002,2:626-630
[115] T. Tomohide, S. Kazuhiro, H. Shiro. A New Level-shifting technique by divided RESURFstructure[C]. Power Semiconductor Devices and IC's(ISPSD), Weimar,1997,57-60
[116] X. B. Chen. Method of producing a low-voltage power supply in a power integrated circuit [P].US Patent,7701006,2010(或陈星弼.低压电源[P].中国,发明专利, CN101719721A,2010年6月2)
[117] V. Gupta, G. A. Rincón-Mora. A low dropout, CMOS regulator with high psr over widebandfrequencies[C]. International Symposium on Circuits and Systems,Kobe,2005,5:4245-4248
[118] Q.Li, J.Jiang, J. Wang, et al.. A CMOS low-noise, low-dropout regulator[C]. Power andEnergy Engineering Conference, Chengdu,2010,1-4
[119] J. Z. Liu, X. B. Chen. A new level-shifting structure with multiply metal rings by dividedRESURF technique[J], Journal of Semiconductors,2009,30(4):044005-1～044005-4
[120] X. B. Chen.Semiconductor device [P], U.S. papent,8134206B2, Jan.8,2010(或陈星弼.一种半导体器件[P].中国,发明专利, CN101442052,2009年05月27日)
[121] S. L. Kim, C. K Jeon, M. S. Kim, et al..1200V interconnection technique with isolatedself-shielding structure[C]. In Proc.18thISPSD, Naples,2006,1-4
[122] J. Zhu, Q. Qian, W. Sun, S. et al.. A novel compact isolated structure for600v gate drive IC[C].International Conference of Electron Devices and Solid-State Circuits, Tianjin,2011,1-2
[123] W. Sun, J. Zhu, Q. Qian, et al.. A novel double-well isolation structure for high voltage ICs[C].In Proc.24thISPSD, Bruges,2012,193-196
[124] K. Shimizu, T. Terashima. The2nd Generation divided Resurf structure for High VoltageICs[C]. In Proc.20thISPSD, Orlando,2008,311-314
[125] M. Yamaji, K. Abe, T. Maiguma, et al.. A novel600V-LDMOS with HV-interconnection forHVIC on thick SOI[C]. In Proc.22ndISPSD, San Diego,2010,101-104
[126] T. K. Starke, P. M. Holland, S. Hussain, et al.. Highly effective junction isolation structures forPICs based on standard CMOS process[J].IEEE Transactions on Electron Devices,2004,51(7):1178-1184
[127] A. Nakagawa. Impact of dielectric isolation technology on power ICs[C]. In3rdInternationalSymposium on Power Semiconductor Devices and ICs, Baltimore,1991,16-21
[128] SOI in action, into high gear [OL], http://www.advancedsubstratenews.com/2008/12/into-high-gear/, December3,2008
[129] J. M. Park. Novel Power devices for smart power applications[DB], sterreich: TechnischeUniversit t Wien. http://www.iue.tuwien.ac.at/phd/park/,2004
[130] J. Weyers, H. Vogt. A50V smart power process with dielectric isolation by SIMOX[C].In International Electron Devices Meeting, San Francisco,1992,225-228
[131] J. Adamic, W. Fred Inverted dielectric isolation process [P]. U.S. Patent,5841197,Sep.5,1998
[132] A. Nakagawa, Y. Yamaguchi, T. Ogura, et al..500V three phase inverter ICs based on a newdielectric isolation technique[C]. In Proc. ISPSD, Tokyo,1992,328-332
[133] K. Lehovec.Invention of p-n junction isolation in integrated circuits[J].IEEE Transactions onElectron Devices,1978,25(4):495-496
[134] BCDlite–The ideal green power management platform[OL]. http://www.globalfoundries.com/newsletter/2011/2/bcdlite.aspx, Winter2011
[135] M. B. Vora. A self-isolation scheme for integrated circuits[J]. IBM Journal of Research andDevelopment,1971,15(6):430-435
[136]杨春. SOI高压集成电路的隔离技术研究[D].成都:电子科技大学,2006
[137]刘刚,何笑明,陈涛.微电子器件与IC设计[M].北京:科学出版社，2005:261-262
[138] S. Pawel, M. Ro berg, R. Herzer.600V SOI gate drive HVIC for medium power applicationsoperating up to200C[C]. In17thISPSD, Santa Barbara,2005,55-58
[139] M. Ro berg, B. Vogler, R. Herzer.600V SOI gate driver IC with advanced level shifterconcepts for medium and high power applications[C]. In2007European Conference on PowerElectronics and Applications, Aalborg,2007,1-8
[140] M. Robberg, H. Reinhard, P. Sascha. Latch-up free600V SOI gate driver IC for mediumpower and high temperature applications[C]. In European Conference on Power Electronicsand Applications, Europe,2005,1-10
[141] B. Vogler, M. Rossberg, R. Herzer, et al..600V Converter/Inverter/Brake (CIB)-Module withintegrated SOI Gate Driver IC for Medium Power Applications[C]. The5thInternationalConference on Integrated Power Systems (CIPS),2008,1-5
[142] R. Herzer. Integrated Gate Driver Circuit Solutions[C]. The6thInternational Conference onIntegrated Power Electronics Systems (CIPS),2010,1-10
[143] T. Letavic, E. Arnold, M. Simpson, et al.. High performance600V smart power technologybased on thin layer silicon-on-insulator[C]. In International Symposium on PowerSemiconductor Devices and IC's, Weimar,1997,49-52
[144] T. Letavic, M. Simpson, E. Arnold, et al..600V power conversion system-on-a-chip based onthin layer silicon-on-insulator[C]. The11thInternational Symposium on Power SemiconductorDevices and ICs, Toronto,1999,325-328
[145] T. Letavic, E. Arnold, M. Simpson, et al..600V single-chip power conversion system basedon thin layer silicon-on-insulator[C]. In Proceeding SOI Conference, Stuart,1998,133-134
[146] T. Letavic, J. Petruzzello, M. Simpson, et al.. Lateral smart-discrete process and devices basedon thin-layer silicon-on-insulator[C]. In Proc. ISPSD, Osaka,2001,407-410
[147] K. Endo, Y. Baba, Y. Udo, et al.. A500V1A1-chip inverter IC with a new electric fieldreduction structure[C]. In Proceedings of the6th International Symposium on PowerSemiconductor Devices and ICs, Davos,1994,379-383
[148] M.Yoshino, K. Shimizu, T. Terashima. A new1200V HVIC with a novel high voltagePch-MOS[C]. In22ndInternational Symposium on Power Semiconductor Devices&IC's, SanDiego,2010,93-96
[149] T. Fujihira, Y. Yukio, O. Shigeyuki, et al.. Proposal of new interconnection technique for veryhigh-voltage IC's[J]. Japanese journal of applied physics,1996,35(1):5655-5663
[150] S. Satoshi, T. Shigeki, Y. Akira, et al.. High Voltage and High Reliability Silicon-on-InsulatorPower IC Technologiesand Their Application to750V4.5A Micro-Inverter IC[J].JapaneseJournal of Applied Physics,2012,51:04DP03-1-4
[151] H. Akiyama, N. Yasuda, J. Moritani,et al.. Improved dielectric isolation hvic technology(SODI) in transfer mold package. In Power Semiconductor Devices and IC's[C], IEEEInternational Symposium on ISPSD, Naples,2006,1-4
[152] E. O. Arad, A. Parag, E. Aloni, et al.. Junction isolation for high voltage integrated circuits[C].In27thConvention of Electrical&Electronics Engineers in Israel (IEEEI), Eilat,2012,1-4
[153] T. Yamazaki, N. Kumagai, K. Oyabe, et al.. New high voltage integrated circuits usingself-shielding technique[C]. The11thInternational Symposium on Power SemiconductorDevices and ICs, Toronto,1999,333-336
[154] T. Fujihira, Y. Yano, S. Obinata, et al.. Self-shielding: new high-voltage inter-connectiontechnique for HVICs[C]. In8thInternational Symposium on Power Semiconductor Devicesand ICs, Maui,1996,231-234
[155]陈星弼.功率MOSFET与高压集成电路[M].南京:东南大学出版社,1990
[156] M. F. Kong, X. B. Chen. A novel isolation method for half-bridge power ICs[J]. IEEETransactions on Electron Devices,2013,60(7):2318-2323
[157] R. Jacob Baker.CMOS: circuit design, layout, and simulation (Third edition)[M]. Wiley-IEEEPress,2010:621-626
[158] R.Jacob Baker,Harry W.Li(著),陈中键(译）.CMOS电路设计·布局与仿真[M].北京:机械工业出版社,2006:325-370
[159] M. F. Kong, X. B. Chen. Novel high-voltage, high-side and low-side power devices with asingle control signal[J]. Journal of Semiconductors,2013,34(9):094009-1～094009-5
[160] C. Hans. Designing Analog Chips-2ndedition[M].USA:Virtualbookworm Publishing,2005
[161] International Rectifier.IR2153self-oscillating half-bridge driver [DB], Date sheet,2005,5-8
[162]章建峰.逆变器死区时问对输出电压的影响分析[J].电子电力技术,2007,8:32-33
[163]俞铁刚.电子镇流器中部分子电路的分析和设计[D].成都:电子科技大学,2004
[164]韦光萍.电子镇流器中部分低压电路的分析与设计[D].成都:电子科技大学,2005
[165] C. Stanescu. A150mA LDO in0.8μm CMOS process[C]. In International SemiconductorConference, Sinaia,2000,1:83-86
[166]王凤歌.一种LDO线性稳压器的研究与设计[D].西安:西北大学,2010
[167]毕查得-拉扎维[著],陈贵灿,程军,张瑞智等[译].模拟CMOS集成电路设计[M],西安:西安交通大学出版社,2003
[168] T. L. Brooks, A. L. Westwick. A low-power differential CMOS bandgap reference[C]. In41stInternational Solid-State Circuits Conference,1994,248-249
[169]陈星弼.一种半导体器件及其提供的低压电源的应用[P].中国,发明专利,CN101281907A,2008年5月14日
[170]孙淑惠.倍压整流电路原理仿真及应用[J].机床电器,2009,36(2),8-10
[171] X. B. Chen. Lateral high-voltage semiconductor devices with majorities of both types forconduction [P], U.S.Patent,8159026, Apr.17,2012(或陈星弼.一种半导体横向器件和高压器件[P].中国,发明专利, CNIO1521203,2009年9月2日)
[172] Y. Wei, G. Gildenblat, C. C. McAndrew. Compact model of impact ionizationin LDMOStransistors[J]. IEEE Transactions on Electron Devices.2012,59(7):1863-1869
[173] P. Hower, J. Lin, S. Pendharkar, et al.. A rugged LDMOS for LBC5technology[C]. In Proc.IEEE ISPSD, Santa Barbara,2005,327-330
[174] J. Lin and P. L. Hower. Two-carrier current saturation in a lateral DMOS[C].In Proc. IEEEISPSD, Naples,2006,1-4
[175] S. Reggiani, G. Baccarani, E. Gnani, et al.. Explanation of the rugged LDMOS behavior bymeans of numerical analysis[J].IEEE Trans. Electron Devices,2009,56(11):2811-2818
[176] S. Reggiani, E. Gnani, A. Gnudi, et al.. Investigation on saturation effects in the ruggedLDMOS transistor[C]. In Proc. ISPSD, Barcelona,2009:208-211
[177] T. Sakuda, N. Sadachika, Y. Oritsuki, et al.. Effect of impact-ionization-generated holes on thebreakdown mechanism in LDMOS devices[C]. In Proc. SISPAD, Coronado,2009,1-4
[178] F. Udrea, A. Popescu, W. I. Milne.3D RESURF double-gate MOSFET: A revolutionary powerdevice concept[J].Electronics Letters1998,34(8):808-809
[179] F. Udrea, A. Popescu, W. Milne. The3D RESURF junction[C]. In International SemiconductorConference, Sinaia,1998,1:141-144
[180] M. Denison, Y. Z. Xie, H. Estl. Investigation of a dual channel N/P-LDMOS and applicationto LDO linear voltage regulation[C]. In Proc. Solid-State Device Research Conference,Europe,2010,277-280
[181] S. Poli, S. Reggiani, R. K. Sharma, et al.. Optimization and Analysis of the Dual n/p-LDMOSDevice[J].IEEE Trans. Electron Devices,2012,59(3):745-753
[182] S. Poli, S. Reggiani, R. K. Sharma, et al.. TCAD optimization of a dual N/P-LDMOStransistor[C]. In Proc. Solid-State Device Research Conference, Helsinki,2011,247-250
[183] M. F. Kong, W. F. Du, X. B. Chen. Study on dual channel n-p-LDMOS power devices withthree terminals[J]. IEEE Transactions on Electron Devices,2013,60(10):3508-3514
[184] M. F. Kong, X. B. Chen. High voltage low side and high side power devices based on VLDtechnique[C]. In Proc.11thInt. Conf. on Solid-State and Integrated Circuit Technology, Xi’an,2012,996-998
[185] C. D. Parikh, R. M. Patrikar. A compact model for the N-well resistor[J].Solid-StateElectronics,1999,43(3):683-685
[186] J. Victory, C. C. McAndrew, J. Hall, M. Zunino. A four-terminal compact model for highvoltage diffused resistors with field plates[J]. IEEE Journal of Solid-State Circuits,1998,33(9):1453-1458
[187] V. Puvvada, V. Srinivasan, V. Gupta. A scalable analytical model for the ESD N-wellresistor[C].In Proc. Electrical Overstress/Electrostatic Discharge Symposium Proceedings,USA,2000,437-445
[188] A. Tanaka, Y. Oritsuki, H. Kikuchihara,et al.. Quasi-2-dimensional compact resistor model forthe drift region in high-voltage LDMOS devices[J]. IEEE Trans. Electron Devices,2011,58(7):2072-2080
[2]王建冈.―电力电子技术‖课程教学初探[J].自动化与仪器仪表,2003,5:54-56
[3]王君.现代电子技术在电力系统中的应用分析[J].黑龙江科技信息,2010,06:1-2
[4]唐击.智能电网背景下大功率电力电子技术的巨大市场机遇[J].电器工业,2009,10:8-11
[5]樊立萍,王忠庆.电力电子技术[M].北京：北京大学出版社,2006,1-2
[6] J. Arai, K. Iba, T. Funabashi, Y. Nakanishi. Power electronics and its applications to renewableenergy in Japan[J]. Circuits and Systems Magazine,2008,8(3):52-66
[7] T. G. Wilson. The evolution of power electronics[J]. IEEE Trans. on Power Electronics,2000,15(3):439-446
[8] William E. Newell. Power electronics—emerging from limbo[J]. IEEE Transa. on IndustryApplications,1974, IA-10(1):7-11
[9] W. Erickson Robert, D. Maksimovic. Fundamentals of power electronics (2ndedition)[M].Publisher: Kluwer Academic,2001, Chapter1:3-4
[10]胡浩.智能功率集成电路中的部分模块研究[D].成都:电子科技大学,2012
[11] B. K. Bose. Recent advances in power electronics[J]. IEEE Transactions on Power Electronics,1992,7(1):2-16
[12] L. Lorenz, G. Deboy, A. Knapp. COOLMOS-a new milestone in high voltage powerMOS[C]. The11thInternational Symposium on Power Semiconductor Devices and ICs,Toronto,1999,3-10
[13]王青峰.基于软开关技术馈能性电子负载的研究[D].重庆:重庆大学.2007:9-10
[14] Y.Jang, M.M. Jovanovic, K.H. Fang, et al.. High-power-factor soft-switched boost converter[J].IEEE Transactions on Power Electronics.2006,21(1):98-104
[15] F. L. Luo, H. Ye, H. R. Muhammad. Digital power electronics and applications [DB], USA:Elsevier Academic Press,2005
[16] M. N. Yoder.Wide bandgap semiconductor materials and devices[J]. IEEE transactions onelectron devices.1996,43(10):1633-1636
[17] Wide bandgap semiconductors: pursuing the promise. Energy efficiency and renewableenergy[DB]. U.S. Department of Energy,April2013
[18] J. Milla′n.Wide band-gap power semiconductor devices[J].IET Circuits Devices Syst.,2007,1(5):372-378
[19] J.W. Kolar, J. Biela, S. Waffler, et al.. Performance trends and limitations of power electronicsystems[C]. The6thInternational Conference on Integrated Power Electronics Systems (CIPS),2010,1-20
[20] C. E. Mullett. A5-year power technology roadmap[C]. The19thIEEE Applied PowerElectronics Conference, Anaheim,2004,1:11-17
[21] L. Lorenz. Technology trends and application challenges of new power semiconductor devices
[DB]. Infineon Technologies,2010,1-8
[22] H. Umida. Power electronics technology trends and prospects[J]. Fuji Electric Journal,2002,75(8):1-5
[23]陈晨.电力电子技术发展动向与应用[J].电力电子.2013,9:53
[24]肖向锋.电力电子器件产业发展战略研究[J].电力电子.2011,1:6-9
[25] M. Kawano, J. Hirose, T. Aihara. Power electronics technology: current status and futureoutlook[J]. Power Electronics Technology,2012,58(4):142-148
[26] J. Arai, K. Iba, T. Funabashi, et al.. Power electronics and its applications to renewable energyin Japan[J]. Circuits and Systems Magazine,2008,8(3):52-66
[27] M. Molinas, O. Skjervheim, P. Andreasen, et al.. Power electronics as grid interface for activelycontrolled wave energy converters[C]. International Conference on Clean Electrical Power,2007,188-195
[28] J. Alok.power electronics and its applications (2ndEdition)[M]. India: Penram InternationalPublishing Pvt. Ltd.,2004
[29] B. Murari, F. Bertotti, G.A. Vignola (Eds.) Smart power ICs: technologies and applications (2ndedition)[M]. Berlin: Springer,2002
[30] B. K. Bose. Recent advances and applications of power electronics and motor drives-introduction and perspective[C]. Annual Conference of IEEE Industrial Electronics,2008,25-27
[31]李肇基.新型功率MOS器件及其应用[J].电子科技导报,1995,12:29-34
[32] Y. Tarui, Y. Hayashi, T. Sekigawa. Diffusion self aligned enhance depletion MOS IC (DSA-ED-MOS-IC)[J], Journal of the Japan Society of Applied Physics,1971,40:193-198
[33]雷珍琳,史中海,裴志军,等.平面栅功率MOS场效应晶体管结构研究进展[J].天津职业技术师范大学学报,2012,22(4):17-20
[34] J. A. Appels, H. M. J. Vaes. High voltage thin layer devices (RESURF devices)[C].1979IEEEInternational Electron Devices Meeting, Washington,1979,25:238-241
[35] A. Parpia, C. A. T. Salama. Optimization of RESURF LDMOS transistors: an analyticalapproach[J]. IEEE Transactions on Electron Devices,1990,37(3):789-796
[36] M. M. De Souza, E. M. S. Narayanan. Double RESURF technology for HVICs[J]. ElectronicsLetters,1996,32(12):1092-1093
[37] Z. Hossain, M. Imam, J. Fulton, et al.. Double-RESURF700V N-channel LDMOS withbest-in-class on-resistance[C]. In14thInternational Symposium on Power SemiconductorDevices and ICs,Sante Fe,2002,137-140
[38] X. B. Chen. Lateral high-voltage devices using an optimized variation lateral doping[J]. Int.J.Electronics,1996,80(3):449-459
[39] T. D. Tsibukis, and E. E. Kriezis. VVMOS power transistors: upper and lower bounds of theon-resistance[J]. Electronics Letters,1981:353-355
[40] E.S. Ammar, T.J. Rodgers. UMOS transistors on (110) silicon[J].IEEE Trans. Electron Devices,1980,27(5):907-914
[41] C. A. T. Salama. A new short channel MOSFET structure (UMOST)[J].Solid-State Electronics1977,20(12):1003-1009
[42] H. W. Collins, B. Pelly, HEXFET, A new power technology cuts on-resistance, boosts ratings[J].Electron Design,1979,17(12):36-37
[43]杨法明,杨发顺,张锗源,等.功率VDMOS器件的研究与发展[J].微纳电子技术,2011,48(10):623-629
[44] X. B. Chen, X. Wang, J. K. Sin. A novel high-voltage sustaining structure with buriedoppositely doped regions[J].IEEE Transactions on Electron Devices.2000,47(6):1280-1285
[45] D. Ueda, H. Takagi, and G. Kano. A new vertical power MOSFET structure with extremelyreduced on-resistance[J]. IEEE Transactions on Electron Devices,1985,32(1):2-6
[46] P. Wang, X. Luo, Y. Jiang, et al.. Ultra-low specific on-resistance vertical double-diffusedmetal—oxide semiconductor with a high-k dielectric-filled extended trench[J].Chinese PhysicsB,2013,22(2):027305-1～027305-6
[47] X. B. Chen. Semiconductor power devices with alternating conductivity type high-voltagebreakdown regions [P]. U.S. Patent,5216275,1Jun.1993
[48] G. Deboy, N. Marz, J. P. Stengl, et al.. A new generation of high voltage MOSFETs breaks thelimit line of silicon[C]. International Electron Devices Meeting, Sanfrancisco,1998,12:683-685
[49] L. Lorenz, I. Zverev, A. Mittal, et al.. CoolMOS-a new approach towards systemminiaturization and energy saving[C]. IEEE Industry Applications Conference,Rome,2000,5:2974-2981
[50]陈星弼.超结器件.电力电子技术[J],2008,42(12):2-7
[51] Yole Développement.Super junction MOSFET business update [OL]. http://www.i-micronews.com/reports/Super-Junction-MOSFET-Business-Update/12/344/, Feb.11,2013
[52] Y. Chen, Y. C. Liang, G. S. Samudra,et al.. Progressive development of superjunction powerMOSFET devices[J]. IEEE Transactions on Electron Devices,2008,55(1),211-219
[53] W. Saito, I. Omura, S. Aida, et al.. Over1000V semi-superjunction MOSFET with ultra-lowon-resistance below the si-limit[C]. In17thInternational Symposium on Power SemiconductorDevices and ICs, Santa Barbara,2005,27-30
[54]佘烁杰,杜倩倩,谢雪松,等. IGBT的进展、应用及其可靠性研究[C].2010第十五届可靠性学术年会论文集,2010,158-163
[55]王正元,宋高升. IGBT技术的发展历史和最新进展[J].电力电子,2004,(2)5:7-12
[56] L. Lindenmuller, R. Alvarez, P. Kleinichen, et al.. Characterization of a6.5kV/500A IGBTmodule in a series resonant converter[C]. In Energy Conversion Congress and Exposition(ECCE), Phoenix,2011,4138-4143
[57] M. M. Bakran, H. G. Eckel. Evolution of IGBT converters for mass transit applications[C].In IEEE Industry Applications Conference, Rome,2000,3:1930-1935
[58] V. Michael, C. Fazio, K. Hugh. Ultracompact pulsed power[J]. Proceedings of the IEEE,2004,92(7):1197-1204
[59]许平. IGBT器件新结构及制造技术的新进展[J].电力电子,2005,(3):21-26
[60] News about application specific power semiconductors part1attack of the IGBT[OL].http://www.analog-eetimes.com/en/application-specific-power-semiconductors-part-1-attack-of-the-igbt.html,July16,2010
[61] J. Yeon, M. Park.第2代FS SA T IGBT可显着减少单端谐振逆变器总损耗[OL].http://www.ednchina.com/ART_8800511843_28_20003_TA_59b45b48.HTM, May7,2013
[62] X. Kang, C. Antonio, S. Enrico, et al.. Characterization and modeling of high-voltagefield-stop IGBTs[J]. IEEE Transactions on Industry Applications,2003,39(4):922-928
[63] K. Oh, J. Lee, K. Lee, et al.. A simulation study on novel field stop IGBTs usingsuperjunction[J]. IEEE Transactions on Electron Devices,2006,53(4):884-890
[64] T. Tetsujiro. Method of manufacturing a semiconductor device of an anode short circuitstructure [P]. U.S. Patent,5286655, Feb.15,1994
[65] M. Saggio, V. Raineri, R. Letor, et al.. Innovative localized lifetime control in high-speedIGBTs[J]. Electron Device Letters,1997,18,(7):333-335
[66] J. Pike, A. Douglas, W. T. Dah Tsang, et al.. IGBT process to produce platinum lifetime control
[P].U.S. Patent,5262336, Nov.16,1993
[67] X. B. Chen. High speed IGBT [P]. U.S. Patent,0219446, Sep.25,2010(或陈星弼.一种高速IGBT [P].中国,发明专利,200910119961.3,2009年7月29日)
[68]于福振,吴玉广.智能功率模块及其应用[J].微电机,2003,1:52-55
[69] Intelligent Power Module Sets New Mark for Power Delivery [OL]. http://www.how2power.com/newsletters/0910/products/p1/index.html, Oct.2009
[70]许艳惠,李晓光,杨树臣.智能功率模块在电力机车中的应用[J].电力电子技术,2010,3:79-81.
[71] G. Majumdar. Recent technologies and trends of power devices[C]. International Workshop onPhysics of Semiconductor Devices,India,2007:787-792
[72]钱小工.Smart功率集成电路[J].半导体情报,1992,01:33-48
[73]李肇基,李鸿雁,方健,等.智能功率集成电路精彩纷呈[J]世界产品与技术,2000,6:12-15
[74]孙伟锋,张波,肖胜安,等.功率半导体器件与功率集成技术的发展现状及展望[J].中国科学:信息科学,2012,42(12):1617-1629
[75]刘继芝.高压电源管理芯片中低压电路用电源的研究[D].成都:电子科技大学,2009
[76] B. J. Baliga. An overview of smart power technology[J]. IEEE Transactions on ElectronDevices,1991,38(7):1568-1575
[77]陈志勇,黄其煜,龚大卫. BCD工艺概述[J].半导体技术,2006,31(9),641-644
[78] I. Park, Y. Choi, K. Ko, et al.. BCD (Bipolar-CMOS-DMOS) technology trends for powermanagement IC[C].2011IEEE8thInternational Conference on Power Electronics and ECCEAsia (ICPE&ECCE),Jenu,2011,318-325
[79]杨银堂,朱海刚. BCD集成电路技术的研究与进展[J],微电子学2006,36(3):315-319
[80] B. Murari, C. Contiero, R. Gariboldi,et al.. Smart power technologies evolution[C].2000IEEEIndustry Applications Conference, Europe,2000,1:10-19
[81] C. Contiero, P. Galbiati, A. Merlini, et al.. Trends and issues in BCD smart powertechnologies[C]. IEEE29thSolid-State Device Research Conference, Leuven,1999,1:111-118
[82] E. Dallago, A. Danioni, G. Ricotti, et al.. Single chip, low supply voltage piezoelectrictransformer controller[C]. IEEE29thSolid-State Circuits Conference,Europe,2003:273-276
[83] P. Wessels, M. Swanenberg, J. Claes, et al.. Advanced100V0.13μm BCD process for nextgeneration automotive applications[C]. IEEE18thInternational Symposium on PowerSemiconductor Devices&ICs, Naples,2006,315-318
[84] C. Contiero, A. Antonio, G. Paola. Roadmap differentiation and emerging trends in BCDtechnology[C]. In Proc. ESSDERC, Firenze,2002,275-282
[85] J. Chery. Sustainable Technology&Leadership[R].Technology report PPT of STMicroelectronics Corp.,2011:17-19
[86] M. Zisa. A smartpower innovative actuator in automotive field[C]. In FourteenthEuropean Solid-State Circuits Conference, Manchester,1988,284-290
[87] M. Melito, S. Palara, S. Sueri, et al.. Modern electronic ignition in VIPower technology[C]. InIEEE Intelligent Vehicles'94Symposium, Monterey,1994,435-437
[88] R. Zambrano, G. Fallico, G. Ferla. High voltage IC with vertical current flow and junctionisolation[C]. In IEEE19thSolid State Device Research Conference, Berlin,1989,523-526
[89] M. Melito, G. Belverde, A. Galluzzo, et al.. Bipolar-MOS monolithic cascode switch inVIPower technology[C].Industry Applications Society Annual Meeting, Denver,1994,1322-1325
[90] A. L. Barbera, A. Randazzo, V. Sueri, et al.. A monolithic electronic driver for fluorescentLAMPs[C]. In16thISPSD, Kitakyushu,2004,329-331
[91] X. B. Chen, Z. Q. Song, Z. J. Li Theory of optimum design of reversed-biased p-njunctionsusing resisitive field plates and variational lateral doping[J],Solid State Electronics,1992,35(9):1365-1370
[92] X. B. Chen. Lateral high-voltage devices using an optimized variational lateral doping[J].International journal of electronics,1996,80(3):449-459
[93] X. Chen, X. Fan. Optimum VLD makes SPIC better and cheaper[C].The6th InternationalConference on Solid-State and Integrated-Circuit Technology, Shanghai,2001,1:104-108
[94] X. B. Chen. Surface voltage sustaining structure for semiconductor devices[P].U.S.Patent,5726469, Mar.10,1998
[95]陈星弼.一种用于半导体器件的表面耐压区[P].中国,发明专利, CN1124408,1996年6月12
[96] Yole Développement. Status of the Power Electronics Industry [OL]. http://www.i-micronews.com/reports/Status-Power-Electronics-Industry/12/305/,August10,2012
[97] Yole Developpement.Power device market to bounce back in2013[OL]. http://www.eetimes.com/design/industrial-control/4410770/Power-device-market-to-bounce-back-in-2013,January20,2013
[98] Yole Développement. IGBT Markets and Application Trends Report, IGBT application growthwill lead the market to$6B+by2018[OL]. http://www.i-micronews.com/reports/IGBT-Markets-Trends/12/371/, June10,2013
[99] Yole Développement. SiC Market2013[OL]. http://www.i-micronews.com/reports/SiC-Market-2013/368/, May25,2013
[100] R. Philippe. Delayed progress hits SiC and GaN power device prospects [DB]. PowerDev.,2013,9:18-20
[101]2012年全球功率半导体市场规模比上年减少11.5％，将从2013年下半年开始复苏
[OL].http://china.nikkeibp.com.cn/news/tren/66063-20130520.html, May21,2013
[102] IMS Research.Market for gan and sic power semiconductors set to rise by factor of18from2012to2022[OL]. http://www.imsresearch.com/press-release/market_for_gan_and_sic_power_semiconductors_set_to_rise_by_factor_of_18_from_2012_to_2022, April24,2013
[103]吴琪乐.电子科技大学微固学院副院长张波谈功率器件[J].半导体信息,2011,6:28-29
[104] MOSFET工艺平台提升功率器件性能[OL]. http://semi.cena.com.cn/2013-02/26/content_186261.htm,2013年2月6日
[105]许力.半桥驱动芯片的分析与设计[D].成都:电子科技大学,2009
[106] T. Mishima, M. Nakaoka. A novel high-frequency transformer-linked soft-switchinghalf-bridge DC–DC converter with constant-frequency asymmetrical PWM scheme[J]. IEEETransactions on Industrial Electronics,2009,56(8):2961-2969
[107]毛兴武,刘雪琴.半桥驱动器IR2155电路的应用[J].广东电子,1996,3:33-35
[108]惠斌.一种高速高压半桥驱动电路的分析与设计[D].西安:西北大学,2010
[109] X. B. Chen. Lateral low-side and high-side high-voltage devices [P]. U.S. Patent,6998681, Feb.14,2006(或陈星弼.横向低侧高压器件及高侧高压器件[P].中国,发明专利, CN1529363,2004年9月15)
[110] D. W. Green, E. M. Sankara Narayanan. Fully isolated high side and low side LIGBTs injunction isolation technology[C]. IEEE International Symposium on Power SemiconductorDevices and IC's, Naples,2006,6:1-4
[111] Y. Takeuchi, Y. Takagi. Power IC having high-side and low-side switches in an SOI structure
[P]. U.S. Patent,5939755,17Aug,1999
[112] Y. Yan, Z. Regan. Dual low voltage IC based high and low side gate drive[C]. NineteenthAnnual IEEE Applied Power Electronics Conference, Austin,2004,2:1033-1038
[113] P. Shihong Park, M. Thomas, A. Jahns. A self-boost charge pump topology for a gate drivehigh-side power supply[J]. IEEE transactions on power electronics,2005,20(2):300-307
[114] J. J. Kim, M. H. Kim, S. L. Kim, et al.. The new high voltage level up shifter for HVIC[C].IEEE33rdAnnual Power Electronics Specialists Conference, Cairns,2002,2:626-630
[115] T. Tomohide, S. Kazuhiro, H. Shiro. A New Level-shifting technique by divided RESURFstructure[C]. Power Semiconductor Devices and IC's(ISPSD), Weimar,1997,57-60
[116] X. B. Chen. Method of producing a low-voltage power supply in a power integrated circuit [P].US Patent,7701006,2010(或陈星弼.低压电源[P].中国,发明专利, CN101719721A,2010年6月2)
[117] V. Gupta, G. A. Rincón-Mora. A low dropout, CMOS regulator with high psr over widebandfrequencies[C]. International Symposium on Circuits and Systems,Kobe,2005,5:4245-4248
[118] Q.Li, J.Jiang, J. Wang, et al.. A CMOS low-noise, low-dropout regulator[C]. Power andEnergy Engineering Conference, Chengdu,2010,1-4
[119] J. Z. Liu, X. B. Chen. A new level-shifting structure with multiply metal rings by dividedRESURF technique[J], Journal of Semiconductors,2009,30(4):044005-1～044005-4
[120] X. B. Chen.Semiconductor device [P], U.S. papent,8134206B2, Jan.8,2010(或陈星弼.一种半导体器件[P].中国,发明专利, CN101442052,2009年05月27日)
[121] S. L. Kim, C. K Jeon, M. S. Kim, et al..1200V interconnection technique with isolatedself-shielding structure[C]. In Proc.18thISPSD, Naples,2006,1-4
[122] J. Zhu, Q. Qian, W. Sun, S. et al.. A novel compact isolated structure for600v gate drive IC[C].International Conference of Electron Devices and Solid-State Circuits, Tianjin,2011,1-2
[123] W. Sun, J. Zhu, Q. Qian, et al.. A novel double-well isolation structure for high voltage ICs[C].In Proc.24thISPSD, Bruges,2012,193-196
[124] K. Shimizu, T. Terashima. The2nd Generation divided Resurf structure for High VoltageICs[C]. In Proc.20thISPSD, Orlando,2008,311-314
[125] M. Yamaji, K. Abe, T. Maiguma, et al.. A novel600V-LDMOS with HV-interconnection forHVIC on thick SOI[C]. In Proc.22ndISPSD, San Diego,2010,101-104
[126] T. K. Starke, P. M. Holland, S. Hussain, et al.. Highly effective junction isolation structures forPICs based on standard CMOS process[J].IEEE Transactions on Electron Devices,2004,51(7):1178-1184
[127] A. Nakagawa. Impact of dielectric isolation technology on power ICs[C]. In3rdInternationalSymposium on Power Semiconductor Devices and ICs, Baltimore,1991,16-21
[128] SOI in action, into high gear [OL], http://www.advancedsubstratenews.com/2008/12/into-high-gear/, December3,2008
[129] J. M. Park. Novel Power devices for smart power applications[DB], sterreich: TechnischeUniversit t Wien. http://www.iue.tuwien.ac.at/phd/park/,2004
[130] J. Weyers, H. Vogt. A50V smart power process with dielectric isolation by SIMOX[C].In International Electron Devices Meeting, San Francisco,1992,225-228
[131] J. Adamic, W. Fred Inverted dielectric isolation process [P]. U.S. Patent,5841197,Sep.5,1998
[132] A. Nakagawa, Y. Yamaguchi, T. Ogura, et al..500V three phase inverter ICs based on a newdielectric isolation technique[C]. In Proc. ISPSD, Tokyo,1992,328-332
[133] K. Lehovec.Invention of p-n junction isolation in integrated circuits[J].IEEE Transactions onElectron Devices,1978,25(4):495-496
[134] BCDlite–The ideal green power management platform[OL]. http://www.globalfoundries.com/newsletter/2011/2/bcdlite.aspx, Winter2011
[135] M. B. Vora. A self-isolation scheme for integrated circuits[J]. IBM Journal of Research andDevelopment,1971,15(6):430-435
[136]杨春. SOI高压集成电路的隔离技术研究[D].成都:电子科技大学,2006
[137]刘刚,何笑明,陈涛.微电子器件与IC设计[M].北京:科学出版社，2005:261-262
[138] S. Pawel, M. Ro berg, R. Herzer.600V SOI gate drive HVIC for medium power applicationsoperating up to200C[C]. In17thISPSD, Santa Barbara,2005,55-58
[139] M. Ro berg, B. Vogler, R. Herzer.600V SOI gate driver IC with advanced level shifterconcepts for medium and high power applications[C]. In2007European Conference on PowerElectronics and Applications, Aalborg,2007,1-8
[140] M. Robberg, H. Reinhard, P. Sascha. Latch-up free600V SOI gate driver IC for mediumpower and high temperature applications[C]. In European Conference on Power Electronicsand Applications, Europe,2005,1-10
[141] B. Vogler, M. Rossberg, R. Herzer, et al..600V Converter/Inverter/Brake (CIB)-Module withintegrated SOI Gate Driver IC for Medium Power Applications[C]. The5thInternationalConference on Integrated Power Systems (CIPS),2008,1-5
[142] R. Herzer. Integrated Gate Driver Circuit Solutions[C]. The6thInternational Conference onIntegrated Power Electronics Systems (CIPS),2010,1-10
[143] T. Letavic, E. Arnold, M. Simpson, et al.. High performance600V smart power technologybased on thin layer silicon-on-insulator[C]. In International Symposium on PowerSemiconductor Devices and IC's, Weimar,1997,49-52
[144] T. Letavic, M. Simpson, E. Arnold, et al..600V power conversion system-on-a-chip based onthin layer silicon-on-insulator[C]. The11thInternational Symposium on Power SemiconductorDevices and ICs, Toronto,1999,325-328
[145] T. Letavic, E. Arnold, M. Simpson, et al..600V single-chip power conversion system basedon thin layer silicon-on-insulator[C]. In Proceeding SOI Conference, Stuart,1998,133-134
[146] T. Letavic, J. Petruzzello, M. Simpson, et al.. Lateral smart-discrete process and devices basedon thin-layer silicon-on-insulator[C]. In Proc. ISPSD, Osaka,2001,407-410
[147] K. Endo, Y. Baba, Y. Udo, et al.. A500V1A1-chip inverter IC with a new electric fieldreduction structure[C]. In Proceedings of the6th International Symposium on PowerSemiconductor Devices and ICs, Davos,1994,379-383
[148] M.Yoshino, K. Shimizu, T. Terashima. A new1200V HVIC with a novel high voltagePch-MOS[C]. In22ndInternational Symposium on Power Semiconductor Devices&IC's, SanDiego,2010,93-96
[149] T. Fujihira, Y. Yukio, O. Shigeyuki, et al.. Proposal of new interconnection technique for veryhigh-voltage IC's[J]. Japanese journal of applied physics,1996,35(1):5655-5663
[150] S. Satoshi, T. Shigeki, Y. Akira, et al.. High Voltage and High Reliability Silicon-on-InsulatorPower IC Technologiesand Their Application to750V4.5A Micro-Inverter IC[J].JapaneseJournal of Applied Physics,2012,51:04DP03-1-4
[151] H. Akiyama, N. Yasuda, J. Moritani,et al.. Improved dielectric isolation hvic technology(SODI) in transfer mold package. In Power Semiconductor Devices and IC's[C], IEEEInternational Symposium on ISPSD, Naples,2006,1-4
[152] E. O. Arad, A. Parag, E. Aloni, et al.. Junction isolation for high voltage integrated circuits[C].In27thConvention of Electrical&Electronics Engineers in Israel (IEEEI), Eilat,2012,1-4
[153] T. Yamazaki, N. Kumagai, K. Oyabe, et al.. New high voltage integrated circuits usingself-shielding technique[C]. The11thInternational Symposium on Power SemiconductorDevices and ICs, Toronto,1999,333-336
[154] T. Fujihira, Y. Yano, S. Obinata, et al.. Self-shielding: new high-voltage inter-connectiontechnique for HVICs[C]. In8thInternational Symposium on Power Semiconductor Devicesand ICs, Maui,1996,231-234
[155]陈星弼.功率MOSFET与高压集成电路[M].南京:东南大学出版社,1990
[156] M. F. Kong, X. B. Chen. A novel isolation method for half-bridge power ICs[J]. IEEETransactions on Electron Devices,2013,60(7):2318-2323
[157] R. Jacob Baker.CMOS: circuit design, layout, and simulation (Third edition)[M]. Wiley-IEEEPress,2010:621-626
[158] R.Jacob Baker,Harry W.Li(著),陈中键(译）.CMOS电路设计·布局与仿真[M].北京:机械工业出版社,2006:325-370
[159] M. F. Kong, X. B. Chen. Novel high-voltage, high-side and low-side power devices with asingle control signal[J]. Journal of Semiconductors,2013,34(9):094009-1～094009-5
[160] C. Hans. Designing Analog Chips-2ndedition[M].USA:Virtualbookworm Publishing,2005
[161] International Rectifier.IR2153self-oscillating half-bridge driver [DB], Date sheet,2005,5-8
[162]章建峰.逆变器死区时问对输出电压的影响分析[J].电子电力技术,2007,8:32-33
[163]俞铁刚.电子镇流器中部分子电路的分析和设计[D].成都:电子科技大学,2004
[164]韦光萍.电子镇流器中部分低压电路的分析与设计[D].成都:电子科技大学,2005
[165] C. Stanescu. A150mA LDO in0.8μm CMOS process[C]. In International SemiconductorConference, Sinaia,2000,1:83-86
[166]王凤歌.一种LDO线性稳压器的研究与设计[D].西安:西北大学,2010
[167]毕查得-拉扎维[著],陈贵灿,程军,张瑞智等[译].模拟CMOS集成电路设计[M],西安:西安交通大学出版社,2003
[168] T. L. Brooks, A. L. Westwick. A low-power differential CMOS bandgap reference[C]. In41stInternational Solid-State Circuits Conference,1994,248-249
[169]陈星弼.一种半导体器件及其提供的低压电源的应用[P].中国,发明专利,CN101281907A,2008年5月14日
[170]孙淑惠.倍压整流电路原理仿真及应用[J].机床电器,2009,36(2),8-10
[171] X. B. Chen. Lateral high-voltage semiconductor devices with majorities of both types forconduction [P], U.S.Patent,8159026, Apr.17,2012(或陈星弼.一种半导体横向器件和高压器件[P].中国,发明专利, CNIO1521203,2009年9月2日)
[172] Y. Wei, G. Gildenblat, C. C. McAndrew. Compact model of impact ionizationin LDMOStransistors[J]. IEEE Transactions on Electron Devices.2012,59(7):1863-1869
[173] P. Hower, J. Lin, S. Pendharkar, et al.. A rugged LDMOS for LBC5technology[C]. In Proc.IEEE ISPSD, Santa Barbara,2005,327-330
[174] J. Lin and P. L. Hower. Two-carrier current saturation in a lateral DMOS[C].In Proc. IEEEISPSD, Naples,2006,1-4
[175] S. Reggiani, G. Baccarani, E. Gnani, et al.. Explanation of the rugged LDMOS behavior bymeans of numerical analysis[J].IEEE Trans. Electron Devices,2009,56(11):2811-2818
[176] S. Reggiani, E. Gnani, A. Gnudi, et al.. Investigation on saturation effects in the ruggedLDMOS transistor[C]. In Proc. ISPSD, Barcelona,2009:208-211
[177] T. Sakuda, N. Sadachika, Y. Oritsuki, et al.. Effect of impact-ionization-generated holes on thebreakdown mechanism in LDMOS devices[C]. In Proc. SISPAD, Coronado,2009,1-4
[178] F. Udrea, A. Popescu, W. I. Milne.3D RESURF double-gate MOSFET: A revolutionary powerdevice concept[J].Electronics Letters1998,34(8):808-809
[179] F. Udrea, A. Popescu, W. Milne. The3D RESURF junction[C]. In International SemiconductorConference, Sinaia,1998,1:141-144
[180] M. Denison, Y. Z. Xie, H. Estl. Investigation of a dual channel N/P-LDMOS and applicationto LDO linear voltage regulation[C]. In Proc. Solid-State Device Research Conference,Europe,2010,277-280
[181] S. Poli, S. Reggiani, R. K. Sharma, et al.. Optimization and Analysis of the Dual n/p-LDMOSDevice[J].IEEE Trans. Electron Devices,2012,59(3):745-753
[182] S. Poli, S. Reggiani, R. K. Sharma, et al.. TCAD optimization of a dual N/P-LDMOStransistor[C]. In Proc. Solid-State Device Research Conference, Helsinki,2011,247-250
[183] M. F. Kong, W. F. Du, X. B. Chen. Study on dual channel n-p-LDMOS power devices withthree terminals[J]. IEEE Transactions on Electron Devices,2013,60(10):3508-3514
[184] M. F. Kong, X. B. Chen. High voltage low side and high side power devices based on VLDtechnique[C]. In Proc.11thInt. Conf. on Solid-State and Integrated Circuit Technology, Xi’an,2012,996-998
[185] C. D. Parikh, R. M. Patrikar. A compact model for the N-well resistor[J].Solid-StateElectronics,1999,43(3):683-685
[186] J. Victory, C. C. McAndrew, J. Hall, M. Zunino. A four-terminal compact model for highvoltage diffused resistors with field plates[J]. IEEE Journal of Solid-State Circuits,1998,33(9):1453-1458
[187] V. Puvvada, V. Srinivasan, V. Gupta. A scalable analytical model for the ESD N-wellresistor[C].In Proc. Electrical Overstress/Electrostatic Discharge Symposium Proceedings,USA,2000,437-445
[188] A. Tanaka, Y. Oritsuki, H. Kikuchihara,et al.. Quasi-2-dimensional compact resistor model forthe drift region in high-voltage LDMOS devices[J]. IEEE Trans. Electron Devices,2011,58(7):2072-2080
© 2004-2018 中国地质图书馆版权所有 京ICP备05064691号 京公网安备11010802017129号 地址：北京市海淀区学院路29号 邮编：100083 电话：办公室：(+86 10)66554848；文献借阅、咨询服务、科技查新：66554700 |